As it is known, a monolithically integrated semiconductor electronic device consists of electrically active areas, commonly known as the active areas, and of electrically passive areas, commonly known as isolation areas. Active areas can be classified according to the type of electric structure that they contain. For example, there can be storage areas typically containing memory cells, and circuit areas typically containing transistors, capacitors and resistors.
A block diagram, not to scale, of a monolithically integrated semiconductor electronic device 10 and of advanced generation is shown in FIG. 1 by way of example. This device, which contains memory, circuit, and isolation areas not shown in FIG. 1, typically has at least one circuit area 102 and at least one so-called matrix area 101, the latter comprising a plurality of memory cells being matrix-like arranged. This means that the memory cells are arranged in rows, or word-lines, and columns, or bit-lines.
Associated with this memory cell matrix is a plurality of transistors of the circuit area 102, which forms the control circuitry of the device.
The isolation areas provided in the device 10 have the aim of isolating, electrically and physically, each active area from the others, and of reducing possible parasitic effects. These isolation areas are usually formed simultaneously in different areas of the device 10, and appear in both the matrix and the circuit areas, 101 and 102.
Now, the technology progress presses a demand for reduced size of monolithically integrated semiconductor electronic devices, and this requirement makes it necessary to develop innovative technological solutions, allowing to manufacture of reduced-size devices with satisfactory structural and functional characteristics.
In particular, the isolation areas should have suitable sizes for memory cells in the matrix area 101 to be manufactured with a high density layout. Both the high density memory cells of the matrix area 101 and the transistors of the circuit area 102 must have, on the other side, an optimal behaviour. At present in more advanced technologies, the reduction of isolation structure sizes, necessary to provide the matrix area 101 with high-density memory cells, comes out in a lower reduction of the parasitic effects in the circuit area 102, and in the consequent degradation of the transistor electrical performances. These problems impose manufacture of isolation structures of different thickness according to the device area being considered, a thickness which is to be smaller in the matrix area 101 than in the circuit area 102. These isolation structures of different thickness are defined as differential isolation. Schematic cross-sections, not drawn to scale, of differential isolation structures 20 of the STI (Shallow Trench Isolation) type are shown in FIG. 2, this figure indicating isolation structures 201 of the matrix area 101 alternated with matrix active areas 202, and isolation structures 203 of the circuit area 102 alternated with active circuit areas 204.
A prior art solution to obtain differential isolation structures 20 consists in manufacturing isolation structures, separately and by means of dedicated masks, these structures having different thickness and depths. In detail, this solution is exemplified by STI structures, and comprises the following steps:
A) providing, on a semiconductor material substrate, a succession of dielectric layers, typically made of a silicon oxide or pad oxide layer and a nitride layer;
B) defining, as by lithography and an appropriate resist mask, the active areas 204 of the circuit area 102;
C) anisotropically etching the nitride and pad oxide layers in the circuit area 102;
D) etching silicon, suitable to form STI isolation structures in the circuit area 102;
The steps of forming a succession of dielectric layers (A), of lithographic defining (B), of nitride and pad oxide etching (C) and of silicon etching (D), on a substrate, jointly traces a standard flow process, known as single-isolation process, wherein the isolation structures are formed simultaneously in the matrix area and in the circuit area of the device.
E) removing the resist used in the above lithographic definition;
F) repeating the lithographic defining (B), nitride and pad oxide etching (C), silicon etching (D), and resist removing (E) steps for the matrix area 101. In this case, the silicon etching step (D) must be appropriate to form STI isolation structures which are thinner than the STI isolation structures formed in the circuit area 102. Differential isolation structures 20 are thus provided.
Although advantageous on several counts, this solution has the drawback of requiring the repetition of some process steps with respect to what happens in the standard single-isolation flow process. In particular, the lithographic defining (B), nitride and pad oxide etching (C), silicon etching (D), and resist removing (E) steps in the above exemplary flow process are to be carried out a first time for the circuit area 102 and a second time for the matrix area 101. In addition, in this solution, the mask employed during the lithographic defining step (B) is used a second time. A direct negative consequence of this solution stays in the increased cost and time requirements for manufacturing the isolation structures.
Problems are also brought about by the presence of memory cells inside monolithically integrated semiconductor electronic devices 10 and of advanced generation. For instance, where the memory cells are floating gate non-volatile cells, unevenness of size and thickness often appears in the layers that form the memory cells and transistors, this unevenness affecting the device performance.
An exemplary floating gate non-volatile memory cell, to be typically comprised in the matrix area 101 of the device 10, is schematically shown, in cross section and not to scale, limited to its layers of concern in FIG. 3, where the whole memory cell is indicated with reference number 30. This cell 30 comprises a source region 301, a drain region 302, and a succession of layers forming a gate region globally indicated with reference number 303. The gate region 303 comprises a first or floating gate layer 305 formed above the substrate of semiconductor material and separated from the latter by a thin dielectric layer 304, called tunnel oxide. A second or control gate layer 307 is capacitively coupled to the first floating gate layer 305 by a dielectric layer 306, called interpoly dielectric.
An exemplary transistor 40 of the circuit area 102 is schematically shown, in cross section and not to scale, limited to its layers of concern in FIG. 4.
This transistor typically includes a gate region 303, comprising a gate layer 404 formed above the semiconductor material substrate and separated from the latter by a thin dielectric layer 401, called gate oxide. A source region 402 and a drain region 403 are integrated in the substrate of semiconductor material at the sides of the gate region 303.
As it is well known, the control gate layer 307 and the gate layer 404 are usually formed through a first step (G) of depositing the same polysilicon layer, a second step (I) of lithography defining, and a third step (J) of etching the polysilicon layer.
A problem affecting all monolithically integrated semiconductor electronic devices 10 and of advanced generation, having memory cells 30 in the matrix area 101 and transistors 40 in the circuit area 102, arises in the defining of the polysilicon layer that constitutes the control gate layer 307 and gate layer 404, especially at the boundary of the matrix area 101. In fact the thickness of the layer succession under the polysilicon layer is different in the matrix 101 and circuit 102 area, typically higher in the matrix area 101 because of the presence of the floating gate layer 305 and the interpoly dielectric 306. Thus, the polysilicon layer is bound to be non-planar at the boundary of the matrix area 101. This unevenness causes possible lithographic defining problems resulting in the size and performance of those memory cells 30 which are located at the boundary of the matrix area 101.
A first known solution solves this problem by performing a CMP (Chemical-Mechanical Polishing) step (H) after the polysilicon layer depositing step (G) to reduce the thickness of the polysilicon layer in the matrix area 101. The lithographic defining step (I) of the polysilicon layer and the etching step (J) are then carried out.
However, the above solution can have a drawback, due to the fact that the CMP technique applied during the etching step (H) needs, to be correctly and successfully performed, the layer to be etched to have an almost planar morphology. Accordingly to this solution, the different height of the polysilicon layer in the matrix areas 101 and in the circuit area 102 requires to maintain the polysilicon layer depositing step (G) until an almost planar morphology of the layer itself is achieved. In this way, however, a portion of the polysilicon layer of particularly high thickness is obtained in the circuit area 102, which brings about subsequent doping problems of that polysilicon portion.
A second solution (Patent Application EP 02425311.4) implies the polysilicon depositing step (G) to be followed by a masking step (L) exposing a portion of the polysilicon layer in the matrix area 101. An etching step (M), called etch-back, of the portion of the polysilicon layer in the matrix area 101 and a step (N) of removing the resist used in the above masking step (L) are then carried out. This is followed by the lithographic polysilicon layer defining step (I) and by the etching step (J).
Although achieving its object, also this solution shows integration problems because the etch-back step (M) is hard to control and can easily lead to an excessive reduction of the polysilicon layer thickness of the matrix area 101, with subsequent quality problems of the dielectric layers and possible device malfunctioning.
The technical problem that underlies this invention is to provide a method for manufacturing a monolithically integrated semiconductor electronic device and of advanced generation, with such characteristics as to allow differential isolation structures to be formed and the gate regions accurately defined especially at the boundary of a memory cell matrix, thereby overcoming the limitations and/or drawbacks of prior art methods.